Micromechanical structure with bonded cover

ABSTRACT

A semiconductor layer having an opening and a MEMS resonator formed in the opening is disposed between first and second substrates to encapsulate the MEMS resonator. An electrical contact that extends from the opening to an exterior of the MEMS device is formed at least in part within the semiconductor layer and at least in part within the first substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.16/983,141, filed Aug. 3, 2020, which is a divisional of U.S. patentapplication Ser. No. 16/565,876, filed Sep. 10, 2019 (now U.S. Pat. No.10,766,768), which is a divisional of U.S. patent application Ser. No.16/106,649, filed Aug. 21, 2018 (now U.S. Pat. No. 10,450,190), which isa divisional of U.S. patent application Ser. No. 15/686,480, filed Aug.25, 2017 (now U.S. Pat. No. 10,099,917), which is a divisional of U.S.patent application Ser. No. 15/242,437, filed Aug. 19, 2016 (now U.S.Pat. No. 9,758,371), which is a divisional of U.S. patent applicationSer. No. 14/961,760, filed Dec. 7, 2015 (now U.S. Pat. No. 9,440,845),which is a divisional of U.S. patent application Ser. No. 14/524,986,filed Oct. 27, 2014 (now U.S. Pat. No. 9,434,608). U.S. patentapplication Ser. No. 15/242,437 is also a divisional of U.S. patentapplication Ser. No. 14/524,986, filed Oct. 27, 2014 (now U.S. Pat. No.9,434,608), which is a divisional of U.S. patent application Ser. No.11/593,404, filed Nov. 6, 2006 (now U.S. Pat. No. 8,871,551), which is adivisional of U.S. application Ser. No. 11/336,521, filed Jan. 20, 2006.Each of the foregoing applications is hereby incorporated by reference.

BACKGROUND

There are many inventions described and illustrated herein. Theinventions relate to encapsulation electromechanical structures, forexample, microelectromechanical and/or nanoelectromechanical structure(collectively hereinafter “microelectromechanical structures”) anddevices/systems including same; and more particularly, in one aspect,for fabricating or manufacturing microelectromechanical systems havingmechanical structures that are encapsulated using wafer levelencapsulation techniques, and devices/systems incorporated same.

Microelectromechanical systems, for example, gyroscopes, resonators andaccelerometers, utilize micromachining techniques (i.e., lithographicand other precision fabrication techniques) to reduce mechanicalcomponents to a scale that is generally comparable to microelectronics.Microelectromechanical systems typically include a mechanical structurefabricated from or on, for example, a silicon substrate usingmicromachining techniques.

The mechanical structures are typically sealed in a chamber. Thedelicate mechanical structure may be sealed in, for example, ahermetically sealed metal or ceramic container or bonded to asemiconductor or glass-like substrate having a chamber to house,accommodate or cover the mechanical structure. In the context of thehermetically sealed metal or ceramic container, the substrate on, or inwhich, the mechanical structure resides may be disposed in and affixedto the metal or ceramic container. The hermetically sealed metal orceramic container often also serves as a primary package as well.

In the context of the semiconductor or glass-like substrate packagingtechnique, the substrate of the mechanical structure may be bonded toanother substrate (i.e., a “cover” wafer) whereby the bonded substratesform a chamber within which the mechanical structure resides. In thisway, the operating environment of the mechanical structure may becontrolled and the structure itself protected from, for example,inadvertent contact.

SUMMARY OF AT LEAST ONE OF MULTIPLE DISCLOSED EMBODIMENTS

There are many inventions described and illustrated herein. The presentinventions are neither limited to any single aspect nor embodimentthereof, nor to any combinations and/or permutations of such aspectsand/or embodiments. Moreover, each of the aspects of the presentinventions, and/or embodiments thereof, may be employed alone or incombination with one or more of the other aspects of the presentinventions and/or embodiments thereof. For the sake of brevity, many ofthose permutations and combinations will not be discussed separatelyherein.

In one aspect, the present inventions are directed to amicroelectromechanical device comprising a first substrate, a chamber,and a microelectromechanical structure, wherein themicroelectromechanical structure is (i) formed from a portion of thefirst substrate and (ii) at least partially disposed in the chamber. Inaddition, in this aspect, the microelectromechanical device furtherincludes a second substrate, bonded to the first substrate, wherein asurface of the second substrate forms a wall of the chamber, as well asa contact. The contact includes (1) a first portion of the contact is(i) formed from a portion of the first substrate and (ii) at least aportion thereof is disposed outside the chamber, and (2) a secondportion of the contact is formed from a portion of the second substrate.

In one embodiment, the second substrate includes polycrystallinesilicon, porous polycrystalline silicon, amorphous silicon, siliconcarbide, silicon/germanium, germanium, or gallium arsenide. The firstsubstrate may include polycrystalline silicon, porous polycrystallinesilicon, amorphous silicon, silicon carbide, silicon/germanium,germanium, or gallium arsenide.

In addition, in one embodiment, the first portion of the contact is asemiconductor material having a first conductivity, the second substrateis a semiconductor material having a second conductivity, and the secondportion of the contact is a semiconductor material having the firstconductivity. Notably, the second portion of the contact may be apolycrystalline or monocrystalline silicon that is counterdoped toinclude the first conductivity.

The microelectromechanical device may further include a trench, disposedin the second substrate and around at least a portion of the secondportion of the contact. The trench may include a first material (forexample, an insulation material) disposed therein to electricallyisolate the second portion of the contact from the second substrate.

Notably, the first substrate is a semiconductor on insulator substrate.

In another principle aspect, the present inventions are directed to amicroelectromechanical device comprising a first substrate, a secondsubstrate, wherein the second substrate is bonded to the firstsubstrate, a chamber, and a microelectromechanical structure, whereinthe microelectromechanical structure is (i) formed from a portion of thesecond substrate and (ii) at least partially disposed in the chamber.The microelectromechanical device may further include a third substrate,bonded to the second substrate, wherein a surface of the third substrateforms a wall of the chamber. The microelectromechanical device may alsoinclude a contact having (1) a first portion of the contact is (i)formed from a portion of the second substrate and (ii) at least aportion thereof is disposed outside the chamber, and (2) a secondportion of the contact is formed from a portion of the third substrate.

The second substrate may include polycrystalline silicon, porouspolycrystalline silicon, amorphous silicon, silicon carbide,silicon/germanium, germanium, or gallium arsenide. The third substratemay include polycrystalline silicon, porous polycrystalline silicon,amorphous silicon, silicon carbide, silicon/germanium, germanium, orgallium arsenide.

In one embodiment, the first portion of the contact is a semiconductormaterial having a first conductivity, the third substrate is asemiconductor material having a second conductivity, and the secondportion of the contact is a semiconductor material having the firstconductivity. Notably, in one embodiment, the second portion of thecontact may be a polycrystalline or monocrystalline silicon that iscounterdoped to include the first conductivity.

The microelectromechanical device may further include a trench, disposedin the third substrate and around at least a portion of the secondportion of the contact. The trench may include a first material (forexample, an insulation material) disposed therein to electricallyisolate the second portion of the contact from the third substrate.

The microelectromechanical device may also include an isolation regiondisposed in the second substrate such that the trench is aligned withand juxtaposed to the isolation region. In this embodiment, the firstportion of the contact may be a semiconductor material having a firstconductivity, the isolation region may be a semiconductor materialhaving a second conductivity, and the second portion of the contact maybe a semiconductor material having the first conductivity. A trench maybe included to electrically isolate the second portion of the contactfrom the second substrate. The trench may include a semiconductormaterial, disposed therein, having the second conductivity.

In another embodiment, the microelectromechanical device may include anisolation region disposed in the first substrate such that the firstportion of the contact is aligned with and juxtaposed to the isolationregion.

In yet another embodiment, the microelectromechanical device may includea first isolation region and a second isolation region. The firstisolation region may be disposed in the first substrate such that thefirst portion of the contact is aligned with and juxtaposed to the firstisolation region. The second isolation region may be disposed in thesecond substrate such that the second portion of the contact is alignedwith and juxtaposed to the second isolation region. In this embodiment,the first and second portions of the contact may be semiconductormaterials having a first conductivity, and the first and secondisolation regions may be semiconductor materials having the secondconductivity.

The microelectromechanical device of this embodiment may also include atrench, disposed in the third substrate and around at least a portion ofthe second portion of the contact. The trench may include a firstmaterial (for example, an insulator material) disposed therein toelectrically isolate the second portion of the contact from the thirdsubstrate. The trench may be aligned with and juxtaposed to the secondisolation region.

Notably, all forms of bonding, whether now known or later developed, areintended to fall within the scope of the present invention. For example,bonding techniques such as fusion bonding, anodic-like bonding, silicondirect bonding, soldering (for example, eutectic soldering), thermocompression, thermo-sonic bonding, laser bonding and/or glass reflowbonding, and/or combinations thereof.

Moreover, any of the embodiments described and illustrated herein mayemploy a bonding material and/or a bonding facilitator material(disposed between substrates, for example, the second and thirdsubstrates) to, for example, enhance the attachment of or the “seal”between the substrates (for example, the first and second, and/or thesecond and third), address/compensate for planarity considerationsbetween substrates to be bonded (for example, compensate for differencesin planarity between bonded substrates), and/or to reduce and/orminimize differences in thermal expansion (that is materials havingdifferent coefficients of thermal expansion) of the substrates andmaterials therebetween (if any). Such materials may be, for example,solder, metals, frit, adhesives, BPSG, PSG, or SOG, or combinationsthereof.

Again, there are many inventions, and aspects of the inventions,described and illustrated herein. This Summary of the Inventions is notexhaustive of the scope of the present inventions. Moreover, thisSummary of the Inventions is not intended to be limiting of theinventions and should not be interpreted in that manner. While certainembodiments have been described and/or outlined in this Summary of theInventions, it should be understood that the present inventions are notlimited to such embodiments, description and/or outline, nor are theclaims limited in such a manner. Indeed, many others embodiments, whichmay be different from and/or similar to, the embodiments presented inthis Summary, will be apparent from the description, illustrations andclaims, which follow. In addition, although various features, attributesand advantages have been described in this Summary of the Inventionsand/or are apparent in light thereof, it should be understood that suchfeatures, attributes and advantages are not required whether in one,some or all of the embodiments of the present inventions and, indeed,need not be present in any of the embodiments of the present inventions.

BRIEF DESCRIPTION OF THE DRAWINGS

In the course of the detailed description to follow, reference will bemade to the attached drawings. These drawings show different aspects ofthe present inventions and, where appropriate, reference numeralsillustrating like structures, components, materials and/or elements indifferent figures are labeled similarly. It is understood that variouscombinations of the structures, components, materials and/or elements,other than those specifically shown, are contemplated and are within thescope of the present inventions.

FIG. 1A is a block diagram representation of a mechanical structuredisposed on a substrate and encapsulated via at least a secondsubstrate;

FIG. 1B is a block diagram representation of a mechanical structure andcircuitry, each disposed on one or more substrates and encapsulated viaa substrate;

FIG. 2 illustrates a top view of a portion of a mechanical structure ofa conventional resonator, including moveable electrode, fixed electrode,and a contact;

FIG. 3 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the first substrate employs an SOI wafer;

FIGS. 4A-4G illustrate cross-sectional views (sectioned along dottedline A-A′ of FIG. 2 ) of the fabrication of the mechanical structure ofFIGS. 2 and 3 at various stages of an exemplary process that employs anencapsulation technique according to certain aspects of the presentinventions;

FIG. 5 illustrates a cross-sectional view (sectioned along dotted lineA-A′ of FIG. 2 ) of a portion of the moveable electrode, fixedelectrode, and the contact of FIG. 2 , wherein microelectromechanicalsystem includes electronic or electrical circuitry in conjunction withmicromachined mechanical structure of FIG. 2 , in accordance with anexemplary embodiment of the present inventions;

FIGS. 6A-6D illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 5 at various stagesof an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIGS. 7A-7C, and 8A and 8B illustrate cross-sectional views of twoexemplary embodiments of the fabrication of the portion of themicroelectromechanical system of FIG. 5 using processing techniqueswherein electronic or electrical circuitry (at various stages ofcompleteness) is formed in the second substrate prior to encapsulatingthe mechanical structure via securing the second substrate to the firstsubstrate;

FIG. 9 illustrates a cross-sectional view (sectioned along dotted lineA-A′ of FIG. 2 ) of a portion of the moveable electrode, fixedelectrode, and the contact of FIG. 2 , wherein micromachined mechanicalstructure of FIG. 2 includes an isolation trench to electrically isolatethe contact, in accordance with an exemplary embodiment of the presentinventions;

FIGS. 10A-10I illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 9 at various stagesof an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 11 illustrates a cross-sectional view (sectioned along dotted lineA-A′ of FIG. 2 ) of a portion of the moveable electrode, fixedelectrode, and the contact of FIG. 2 , wherein micromachined mechanicalstructure of FIG. 2 includes isolation regions and an isolation trench(aligned therewith) to electrically isolate the contact, in accordancewith an exemplary embodiment of the present inventions;

FIGS. 12A-12J illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 11 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 13A illustrates a cross-sectional view (sectioned along dotted lineA-A′ of FIG. 2 ) of a portion of the moveable electrode, fixedelectrode, and the contact of FIG. 2 , wherein micromachined mechanicalstructure of FIG. 2 includes isolation regions and an isolation trench(aligned therewith), including an oppositely doped semiconductor(relative to the conductivity of second substrate 14 b), to electricallyisolate the contact, in accordance with an exemplary embodiment of thepresent inventions;

FIGS. 13B and 13C illustrate cross-sectional views of the fabrication ofthe portion of the microelectromechanical system of FIG. 13A at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 14 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an embodiment of the present inventions whereinthe microelectromechanical system employs three substrates;

FIGS. 15A-15H illustrate cross-sectional views (sectioned along dottedline A-A′ of FIG. 2 ) of the fabrication of the mechanical structure ofFIGS. 2 and 14 at various stages of a process that employs anencapsulation technique according to certain aspects of the presentinventions;

FIG. 16 illustrates a cross-sectional view of an embodiment of thefabrication of the microelectromechanical system of FIG. 14 whereinelectronic or electrical circuitry (after fabrication) is formed in thethird substrate according to certain aspects of the present inventions;

FIG. 17 illustrates a cross-sectional view of an exemplary embodiment ofthe present inventions of the microelectromechanical system including aplurality of micromachined mechanical structures wherein a firstmicromachined mechanical structure is formed in the second substrate anda second micromachined mechanical structure is formed in the thirdsubstrate wherein a fourth substrate encapsulates one or more of themicromachined mechanical structures according to certain aspects of thepresent inventions;

FIG. 18 illustrates a cross-sectional view of an exemplary embodiment ofthe present inventions of the microelectromechanical system including aplurality of micromachined mechanical structures wherein a firstmicromachined mechanical structure is formed in the second substrate anda second micromachined mechanical structure is formed in the thirdsubstrate wherein a fourth substrate encapsulates one or more of themicromachined mechanical structures and includes electronic orelectrical circuitry according to certain aspects of the presentinventions;

FIG. 19 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates and cavities are formed in the first and third substrates;

FIGS. 20A-20H illustrate cross-sectional views (sectioned along dottedline A-A′ of FIG. 2 ) of the fabrication of the mechanical structure ofFIGS. 2 and 19 at various stages of an exemplary process that employs anencapsulation technique according to certain aspects of the presentinventions;

FIG. 21 illustrates a cross-sectional view (sectioned along dotted lineA-A′ of FIG. 2 ) of a portion of the moveable electrode, fixedelectrode, and the contact of FIG. 2 , wherein the first cavity isformed in the second substrate and a second cavity is formed in a thirdsubstrate according to certain aspects of the present inventions;

FIG. 22 illustrates a cross-sectional view (sectioned along dotted lineA-A′ of FIG. 2 ) of a portion of the moveable electrode, fixedelectrode, and the contact of FIG. 2 , wherein the first and secondcavities are formed in the second substrate, according to certainaspects of the present inventions;

FIG. 23 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates and the second and third substrates include the sameconductivity types;

FIGS. 24A-24I illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 23 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 25 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates and the first and second substrates include the sameconductivity types;

FIGS. 26A-26H illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 25 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 27 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates which include the same conductivity types;

FIGS. 28A-28I illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 27 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 29 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates which include the same conductivity types;

FIGS. 30A-30I illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 29 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIGS. 31A-31D illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 27 at variousstages of an exemplary process that employs grinding and/or polishing toprovide a desired surface, according to certain aspects of the presentinventions;

FIG. 32 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates;

FIGS. 33A-33I illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 32 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 34 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates wherein an insulative layer is disposed between each of thesubstrates;

FIGS. 35A-35L illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 34 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 36 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates wherein an insulative layer is disposed between two of thesubstrates;

FIGS. 37A-37I illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 36 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 38 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates wherein an insulative layer is disposed between two of thesubstrates and isolation trenches and regions electrically isolate thecontact;

FIGS. 39A-39K illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 38 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 40 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates wherein an intermediate layer (for example, a native oxidelayer) is disposed between two of the substrates;

FIGS. 41A-41H illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 40 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIGS. 42A and 42B are cross-sectional views (sectioned along dotted lineA-A′ of FIG. 2 ) of a portion of the moveable electrode, fixedelectrode, and the contact of FIG. 2 of exemplary embodiments of thepresent inventions wherein the microelectromechanical system employsthree substrates wherein an intermediate layer (for example, a nativeoxide layer) is disposed (for example, deposited or grown) between twoof the substrates;

FIGS. 43A-43K illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical systems of FIGS. 42A and 42B atvarious stages of an exemplary process that employs an encapsulationtechnique according to certain aspects of the present inventions;

FIG. 44 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates and the processing techniques include alternative processingmargins;

FIGS. 45A-45I illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 44 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 46A is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates and the processing techniques include alternative processingmargins wherein the isolation trenches include an over etch;

FIG. 46B is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates and a selected trench includes alternative processingmargins;

FIGS. 47A-47D and 48A-48C are cross-sectional view (sectioned alongdotted line A-A′ of FIG. 2 ) of a portion of the moveable electrode,fixed electrode, and the contact of FIG. 2 of an embodiment of thepresent inventions having alternative exemplary processing techniques,flows and orders thereof;

FIGS. 49A-49G, 50A-50G and 51A-51J are cross-sectional views (sectionedalong dotted line A-A′ of FIG. 2 ) of a portion of the moveableelectrode, fixed electrode, and the contact of FIG. 2 of exemplaryembodiments of the present inventions having alternative processingtechniques, flows and orders thereof relative to one or more ofsubstrates;

FIG. 52 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates wherein isolation regions are implanted in a cover substrateto electrically isolate the contact;

FIGS. 53A-53H illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 52 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 54 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein the microelectromechanical system employs threesubstrates wherein isolation regions include an insulation material (forexample, a silicon nitride or silicon dioxide);

FIGS. 55A-55K illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 54 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 56 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein a contact area is etched and formed in one of the“cover” substrate to provide for electrical conductivity with the anunderlying contact area;

FIGS. 57A-57J illustrate cross-sectional views of an exemplary flow ofthe fabrication of the portion of the microelectromechanical system ofFIG. 56 at various stages of an exemplary process that employs anencapsulation technique according to certain aspects of the presentinventions;

FIG. 58 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of an exemplary embodiment of the presentinventions wherein bonding material and/or a bonding facilitatormaterial is employed between substrates;

FIGS. 59A-59J illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 58 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIG. 60 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2 ) of a portion of the moveable electrode, fixed electrode, andthe contact of FIG. 2 of another exemplary embodiment of the presentinventions wherein bonding material and/or a bonding facilitatormaterial is employed between substrates;

FIGS. 61A-61K illustrate cross-sectional views of the fabrication of theportion of the microelectromechanical system of FIG. 58 at variousstages of an exemplary process that employs an encapsulation techniqueaccording to certain aspects of the present inventions;

FIGS. 62-64 illustrates cross-sectional views of several embodiments ofthe fabrication of microelectromechanical systems of the presentinventions wherein the microelectromechanical systems include electronicor electrical circuitry formed in a substrate, according to certainaspects of the present inventions; and

FIGS. 65 and 66A-66F are block diagram illustrations of variousembodiments of the microelectromechanical systems of the presentinventions wherein the microelectromechanical systems includes at leastthree substrates wherein one or more substrates include one or moremicromachined mechanical structures and/or electronic or electricalcircuitry, according to certain aspects of the present inventions.

DETAILED DESCRIPTION

There are many inventions described and illustrated herein. In oneaspect, the present inventions relate to devices, systems and/or methodsof encapsulating and fabricating electromechanical structures orelements, for example, accelerometer, gyroscope or other transducer (forexample, pressure sensor, strain sensor, tactile sensor, magnetic sensorand/or temperature sensor), filter or resonator The fabricating ormanufacturing microelectromechanical systems of the present invention,and the systems manufactured thereby, employ wafer bonding encapsulationtechniques.

With reference to FIGS. 1A, 1B and 2 , in one exemplary embodiment,microelectromechanical device 10 includes micromachined mechanicalstructure 12 that is disposed on substrate 14, for example, asemiconductor, a glass, or an insulator material. Themicroelectromechanical device 10 may include electronics or electricalcircuitry 16 (hereinafter collectively “circuitry 16”) to, for example,drive mechanical structure 12, sense information from mechanicalstructure 12, process or analyze information generated by, and/orcontrol or monitor the operation of micromachined mechanical structure12. In addition, circuitry 16 (for example, CMOS circuitry) may generateclock signals using, for example, an output signal of micromachinedmechanical structure 12, which may be a resonator type electromechanicalstructure. Under these circumstances, circuitry 16 may include frequencyand/or phase compensation circuitry (hereinafter “compensationcircuitry” or “compensation circuitry 17”), which receives the output ofthe resonator and adjusts, compensates, corrects and/or controls thefrequency and/or phase of the output of resonator. In this regard,compensation circuitry uses the output of resonator to provide anadjusted, corrected, compensated and/or controlled output having, forexample, a desired, selected and/or predetermined frequency and/orphase.

Notably, circuitry 16 may include interface circuitry to provideinformation (from, for example, micromachined mechanical structure 12)to an external device (not illustrated), for example, a computer,indicator/display and/or sensor.

With continued reference to FIGS. 1A, 1B and 2 , micromachinedmechanical structure 12 may include and/or be fabricated from, forexample, materials in column IV of the periodic table, for examplesilicon, germanium, carbon; also combinations of these, for examplesilicon germanium, or silicon carbide; also of III-V compounds forexample gallium phosphide, aluminum gallium phosphide, or other III-Vcombinations; also combinations of III, IV, V, or VI materials, forexample silicon nitride, silicon oxide, aluminum carbide, or aluminumoxide; also metallic silicides, germanides, and carbides, for examplenickel silicide, cobalt silicide, tungsten carbide, or platinumgermanium silicide; also doped variations including phosphorus, arsenic,antimony, boron, or aluminum doped silicon or germanium, carbon, orcombinations like silicon germanium; also these materials with variouscrystal structures, including single crystalline, polycrystalline,nanocrystalline, or amorphous; also with combinations of crystalstructures, for instance with regions of single crystalline andpolycrystalline structure (whether doped or undoped).

As mentioned above, micromachined mechanical structure 12 illustrated inFIG. 2 may be a portion of an accelerometer, gyroscope or othertransducer (for example, pressure sensor, strain sensor, tactile sensor,magnetic sensor and/or temperature sensor), filter or resonator. Themicromachined mechanical structure 12 may also include mechanicalstructures of a plurality of transducers or sensors including one ormore accelerometers, gyroscopes, pressure sensors, tactile sensors andtemperature sensors. In the illustrated embodiment, micromachinedmechanical structure 12 include moveable electrode 18.

With continued reference to FIG. 2 , micromachined mechanical structure12 may also include contact 20 disposed on or in substrate 14 a. Thecontact 20 may provide an electrical path between micromachinedmechanical structure 12 and circuitry 16 and/or an external device (notillustrated). The contact 20 may include and/or be fabricated from, forexample, a semiconductor or conductive material, including, for example,silicon, (whether doped or undoped), germanium, silicon/germanium,silicon carbide, and gallium arsenide, and combinations and/orpermutations thereof. Notably, micromachined mechanical structure 12 andcircuitry 16 may include multiple contacts 20.

In one embodiment, the present inventions employ two or more substratesto form and encapsulate micromachined mechanical structure 12. Forexample, with reference to FIG. 3 , in one embodiment,microelectromechanical system 10 includes semiconductor on insulator(“SOI”) substrate 14 a and cover substrate 14 b. Briefly, by way ofoverview, in this embodiment, micromachined mechanical structure 12(including moveable electrode 18 and contact 20) is formed in or on SOIsubstrate 14 a and encapsulated via cover substrate 14 b. In thisregard, micromachined mechanical structure 12 is formed in thesemiconductor portion of SOI substrate 14 a that resides on theinsulator portion of SOI substrate 14 a. Thereafter, substrate 14 b issecured (for example, bonded) to the exposed surface of thesemiconductor portion of SOI substrate 14 a to encapsulate micromachinedmechanical structure 12.

In particular, with reference to FIG. 4A, microelectromechanical system10 is formed in or on SOI substrate 14 a. The SOI substrate 14 a mayinclude first substrate layer 22 a (for example, a semiconductor (suchas silicon), glass or sapphire), insulation layer 22 b (for example, asilicon dioxide or silicon nitride layer) and first semiconductor layer22 c (for example, a materials in column IV of the periodic table, forexample silicon, germanium, carbon, as well as combinations of suchmaterials, for example silicon germanium, or silicon carbide). In oneembodiment, SOI substrate 14 a is a SIMOX wafer. Where SOI substrate 36is a SIMOX wafer, such wafer may be fabricated using well-knowntechniques including those disclosed, mentioned or referenced in U.S.Pat. Nos. 5,053,627; 5,080,730; 5,196,355; 5,288,650; 6,248,642;6,417,078; 6,423,975; and 6,433,342 and U.S. Published PatentApplications 2002/0081824 and 2002/0123211, the contents of which arehereby incorporated by reference.

In another embodiment, SOI substrate 14 a may be a conventional SOIwafer having a relatively thin semiconductor layer 22 c. In this regard,SOI substrate 36 having a relatively thin semiconductor layer 22 c maybe fabricated using a bulk silicon wafer which is implanted and oxidizedby oxygen to thereby form a relatively thin silicon dioxide layer 22 bon a monocrystalline wafer surface 22 a. Thereafter, another wafer(illustrated as layer 22 c) is bonded to layer 22 b. In this exemplaryembodiment, semiconductor layer 22 c (i.e., monocrystalline silicon) isdisposed on insulation layer 22 b (i.e. silicon dioxide), having athickness of approximately 350 nm, which is disposed on a firstsubstrate layer 22 a (for example, monocrystalline silicon), having athickness of approximately 190 nm.

Notably, all techniques for providing or fabricating SOI substrate 14 a,whether now known or later developed, are intended to be within thescope of the present inventions.

With reference to FIGS. 4A and 4B, an exemplary method of fabricating orforming micromachined mechanical structure 12 according to thisembodiment of the present inventions may begin with forming first cavity24 in semiconductor layer 22 c using well-known lithographic and etchingtechniques. In this way, a selected portion of semiconductor layer 22 c(for example, 11 μm) is removed to form first cavity 24 (which forms aportion of the chamber in which the mechanical structure, for example,moveable electrode 18, resides).

With reference to FIGS. 4C and 4D, thereafter, moveable electrode 18 andcontact area 26 are formed in semiconductor layer 22 c and moveableelectrode 18 is “released” from insulation layer 22 b. In this regard,trenches 28 a-c are formed in semiconductor layer 22 c to definemoveable electrode 18 and contact area 26 therefrom. (See, FIG. 4C). Thetrenches 28 a-c may be formed using well-known deposition andlithographic techniques. Notably, all techniques for forming orfabricating trenches 28 a-c, whether now known or later developed, areintended to be within the scope of the present inventions.

After moveable electrode 18 is defined via trenches 28 b and 28 c,moveable electrode 18 may be “released” by etching portions ofinsulation layer 22 b that are disposed under moveable electrode 18. Forexample, in one embodiment, where insulation layer 22 b is comprised ofsilicon dioxide, selected portions may be removed/etched usingwell-known wet etching techniques and buffered HF mixtures (i.e., abuffered oxide etch) or well-known vapor etching techniques using vaporHF. The trenches 28 b and 28 c, in addition to defining the features ofmoveable electrode 18, may also permit etching and/or removal of atleast selected portions of insulation layer 22 b thereby providing avoid or cavity 30 beneath moveable electrode 18. (See, FIG. 4D). Properdesign of mechanical structures 12 (and in particular moveable electrode18) and control of the HF etching process parameters may permitinsulation layer 22 b to be sufficiently removed or etched to releasemoveable electrode 18 and permit proper operation of micromachinedmechanical structure 12 and microelectromechanical system 10. Notably,cavities 24 and 30 form the chamber in which the mechanical structure,for example, moveable electrode 18, resides.

With reference to FIG. 4E, second substrate 14 b may be fixed to theexposed portion(s) of semiconductor layer 22 c. The second substrate 14b may be secured to the exposed portion(s) of semiconductor layer 22 cusing, for example, well-known bonding techniques such as fusionbonding, anodic-like bonding and/or silicon direct bonding. Otherbonding technologies are suitable including soldering (for example,eutectic soldering), thermo compression bonding, thermo-sonic bonding,laser bonding and/or glass reflow, and/or combinations thereof. Indeed,all forms of bonding, whether now known or later developed, are intendedto fall within the scope of the present invention.

In conjunction with securing second substrate 14 b to the exposedportion(s) of semiconductor layer 22 c, the atmosphere (including itscharacteristics) in which moveable electrode 18 operates may also bedefined. In this regard, the chamber in which the moveable electrode 18reside may be defined when second substrate 14 b is secured and/or fixedto the exposed portion(s) of semiconductor layer 22 c or after furtherprocessing (for example, an annealing step may be employed to adjust thepressure). Notably, all techniques of defining the atmosphere, includingthe pressure thereof, during the process of securing second substrate 14b to semiconductor layer 22 c, whether now known or later developed, areintended to be within the scope of the present inventions.

For example, second substrate 14 b may be secured to the exposedportion(s) of semiconductor layer 22 c in a nitrogen, oxygen and/orinert gas environment (for example, helium). The pressure of the fluid(gas or vapor) may be selected, defined and/or controlled to provide asuitable and/or predetermined pressure of the fluid in the chamberimmediately after fixing substrate 14 b to the exposed portion(s) ofsemiconductor layer 22 c (in order to avoid damaging portions ofmicromachined mechanical structure 12), after one or more subsequentprocessing steps (for example, an annealing step) and/or aftercompletion of micromachined mechanical structure 12 and/ormicroelectromechanical system 10.

Notably, the gas(es) employed during these processes may providepredetermined reactions (for example, oxygen molecules may react withsilicon to provide a silicon oxide). All such techniques are intended tofall within the scope of the present inventions.

The second substrate 14 b may be formed from any material now known orlater developed. In a preferred embodiment, second substrate 14 bincludes or is formed from, for example, materials in column IV of theperiodic table, for example silicon, germanium, carbon; alsocombinations of these, for example silicon germanium, or siliconcarbide; also of III-V compounds for example gallium phosphide, aluminumgallium phosphide, or other III-V combinations; also combinations ofIII, IV, V, or VI materials, for example silicon nitride, silicon oxide,aluminum carbide, or aluminum oxide; also metallic silicides,germanides, and carbides, for example nickel silicide, cobalt silicide,tungsten carbide, or platinum germanium silicide; also doped variationsincluding phosphorus, arsenic, antimony, boron, or aluminum dopedsilicon or germanium, carbon, or combinations like silicon germanium;also these materials with various crystal structures, including singlecrystalline, polycrystalline, nanocrystalline, or amorphous; also withcombinations of crystal structures, for instance with regions of singlecrystalline and polycrystalline structure (whether doped or undoped).

Before or after second substrate 14 b is secured to the exposedportion(s) of semiconductor layer 22 c, contact area 26 b may be formedin a portion of second substrate 14 b to be aligned with, connect to oroverlie contact area 26 a in order to provide suitable, desired and/orpredetermined electrical conductivity (for example, N-type or P-type)with contact area 26 a when second substrate 14 b is secured to firstsubstrate 14 a. (See, FIG. 4F). The contact area 26 b may be formed insecond substrate 14 b using well-known lithographic and dopingtechniques. In this way, contact area 26 b may be a highly doped regionof second substrate 14 b which provides enhanced electrical conductivitywith contact area 26 a.

Notably, contact area 26 b may be a counter-doped region or heavilycounter-doped region of second substrate 14 b which includes aconductivity that is different from the conductivity of the otherportions of second substrate 14 b. In this way, contact areas 26 a and26 b are electrically isolated from the other portions of secondsubstrate 14 b. Thus, in this embodiment, semiconductor layer 22 c maybe a first conductivity type (for example, an N-type conductivity whichmay be provided, for example, via introduction of phosphorous and/orarsenic dopant(s), among others) and second substrate 14 b may be asecond conductivity type (for example, a P-type conductivity which maybe provided, for example, via introduction of boron dopant(s), amongothers). As such, contact area 26 b may be a counter-doped region orheavily counter-doped N-type region which provides suitable, desiredand/or predetermined electrical conductivity characteristics when secondsubstrate 14 b is secured to first substrate 14 a and contact areas 26 aand 26 b are in physical and electrical contact.

With reference to FIG. 4G, microelectromechanical system 10 may becompleted by depositing, forming and/or growing insulation layer 32 anda contact opening may be etched to facilitate electricalcontact/connection to contact area 26 b, via conductive layer 34 (forexample, a heavily doped polysilicon, metal (such as aluminum, chromium,gold, silver, molybdenum, platinum, palladium, tungsten, titanium,and/or copper), metal stacks, complex metals and/or complex metalstacks) may then be deposited (and/or formed) to provide the appropriateelectrical connection to contact areas 26 (which includes, in thisexample, contacts areas 26 a and 26 b).

Notably, insulation layer 32 and/or conductive layer 34 may be formed,grown and/or deposited before or after second substrate 14 b is securedto the exposed portion(s) of semiconductor layer 22 c. Under thesecircumstances, when second substrate 14 b is secured to first substrate14 a, the microelectromechanical system 10 may be completed.

The insulating layer 32 may be, for example, silicon dioxide, siliconnitride, BPSG, PSG, or SOG, or combinations thereof. It may beadvantageous to employ silicon nitride because silicon nitride may bedeposited in a more conformal manner than silicon oxide. Moreover,silicon nitride is compatible with CMOS processing, in the event thatmicroelectromechanical system 10 includes CMOS integrated circuits.

Notably, prior to formation, deposition and/or growth of insulationlayer 32 and/or conductive layer 34, additional micromachined mechanicalstructures 12 and/or transistors of circuitry 16 may be formed and/orprovided in second substrate 14 b or in other substrates that may befixed to first substrate 14 a and/or second substrate 14 b. In thisregard, the exposed surface of second substrate 14 b may be a suitablebase upon which integrated circuits (for example, CMOS transistors)and/or micromachined mechanical structures 12 may be fabricated on orin. Such integrated circuits may be fabricated using well-knowntechniques and equipment. For example, with reference to FIG. 5 , in oneembodiment, transistor regions 36, which may be integrated circuits (forexample, CMOS transistors) of circuitry 16, may be provided in secondsubstrate 14 b. The transistor regions 36 may be formed before or aftersecond substrate 14 b is secured (for example, bonded) to firstsubstrate 14 a. In this regard, with reference to FIG. 6A, transistorimplants 38 may be formed using well-known lithographic and implantprocesses, after second substrate 14 b is secured to first substrate 14a and concurrently with the formation of contact area 26 b.

Thereafter, conventional transistor processing (for example, formationof gate and gate insulator 40) may be employed to complete thetransistors of circuitry 16. (See, FIG. 6B). The “back-end” processingof microelectromechanical system 10 (for example, formation, growthand/or deposition of insulation layer 32 and conductive layer 34) may beperformed using the same processing techniques as described above. (See,for example, FIGS. 6C and 6D). In this regard, insulation layer 32 maybe deposited, formed and/or grown and patterned and, thereafter,conductive layer 34 (for example, a heavily doped polysilicon, metal(such as aluminum, chromium, gold, silver, molybdenum, platinum,palladium, tungsten, titanium, and/or copper), metal stacks, complexmetals and/or complex metal stacks) is deposited and/or formed. In theillustrative embodiments, contact 20 is accessed directly by thetransistors of circuitry 16 via conductive layer 34. Here, conductivelayer 34 may be a low resistance electrical path that is deposited andpatterned to facilitate connection of micromachined mechanical structure12 and circuitry 16.

As noted above, the transistors of transistor region 36 may be formedprior to securing second substrate 14 b to first substrate 14 a. (See,for example, FIGS. 7A and 7B). Indeed, all of the “back-end” processing,in addition to formation of the transistors of transistor region 36, maybe completed prior to securing second substrate 14 b to first substrate14 a. (See, for example, FIGS. 8A and 8B).

With reference to FIGS. 9, 10A-10I, 11 and 12A-12J, in anotherembodiment of the present inventions, semiconductor layer 22 c of SOIsubstrate 14 a is the same conductivity as second substrate 14 b. Inthese embodiments, micromachined mechanical structure 12 may includeadditional features to electrically isolate contact 20. For example,with reference to FIG. 9 , in one embodiment, micromachined mechanicalstructure 12 includes isolation trenches 42 a and 42 b that isolatescontact 20 (and contact areas 26 a and 26 b) from portions of secondsubstrate 14 b. The isolation trenches 42 a and 42 b may include aninsulator material, for example, silicon dioxide or silicon nitride.Indeed, as illustrated, material that forms insulation layer 32 may alsobe deposited in isolation trenches 42 a and 42 b. Notably, FIGS. 10A-10Iillustrate an exemplary process flow for fabricatingmicroelectromechanical system 10 of FIG. 9 .

With reference to FIG. 11 , in another exemplary embodiment, isolationregions 44 a and 44 b are deposited and/or implanted into portions ofsemiconductor layer 22 c of SOI substrate 14 a in order to facilitateelectrical isolation of contact 20 after second substrate 14 b issecured or fixed (via, for example, bonding). The isolation regions 44 aand 44 b may be any material or structure that insulates contact 20, forexample, an insulator material and/or an oppositely doped semiconductorregion. FIGS. 12A-12J illustrate an exemplary process flow forfabricating microelectromechanical system 10 of FIG. 11 whereinisolation regions 44 a and 44 b are oppositely doped semiconductorregions and an insulation material is disposed in isolation trenches 42a and 42 b.

FIG. 13A illustrates an exemplary microelectromechanical system 10wherein the isolation regions 44 a and 44 b are oppositely dopedsemiconductor regions (relative to the conductivity of second substrate14 b) and a semiconductor, having a conductivity different from theconductivity of the semiconductor of second substrate 14 b, is disposed(for example using epitaxial deposition techniques) in isolationtrenches 42 a and 42 b. FIGS. 13B and 13C illustrate selected portionsof an exemplary process flow for fabricating microelectromechanicalsystem 10 of FIG. 13A.

Notably, the embodiments of FIGS. 9, 11 and 13A may also includecircuitry 16 disposed in second substrate 14 b. The fabricationtechniques described above and illustrated in FIGS. 5-8B may be employedin the embodiments of FIGS. 9 and 11 . Indeed, prior to or afterformation, deposition and/or growth of insulation layer 32 and/orconductive layer 34, additional micromachined mechanical structures 12and/or transistors of circuitry 16 may be formed and/or provided insecond substrate 14 b or in other substrates that may be fixed to firstsubstrate 14 a and/or second substrate 14 b. For the sake of brevity,those discussions, in connection with the embodiments of FIGS. 9, 11 and13A, will not be repeated.

The present inventions may also employ more than two substrates to formand encapsulate micromachined mechanical structure 12. For example, withreference to FIG. 14 , in one embodiment, microelectromechanical system10 includes first substrate 14 a, second substrate 14 b and thirdsubstrate 14 c. Briefly, by way of overview, in this embodiment,micromachined mechanical structure 12 (including moveable electrode 18and contact 20) is formed in second substrate 14 b and encapsulated viathird substrate 14 c. In this regard, micromachined mechanical structure12 is formed in a portion of substrate 14 b. Thereafter, substrate 14 cis secured (for example, bonded) to exposed surface of substrate 14 b toencapsulate micromachined mechanical structure 12. In this embodiment,the portion of substrate 14 b in which micromachined mechanicalstructure 12 is formed includes a conductivity that is different fromthe conductivity of the semiconductor of first substrate 14 a and thirdsubstrate 14 c.

With reference to FIGS. 15A and 15B, an exemplary method of fabricatingor forming micromachined mechanical structure 12 according to thisembodiment of the present inventions may begin with forming first cavity24 in first substrate 14 a using well-known lithographic and etchingtechniques. In one exemplary embodiment, first cavity 24 includes adepth of about 11 μm.

With reference to FIGS. 15C and 15D, second substrate 14 b may be fixedto first substrate 14 a. The second substrate 14 b may be secured to theexposed portion(s) of first substrate 14 a using, for example,well-known bonding techniques such as fusion bonding, anodic-likebonding and/or silicon direct bonding. As mentioned above, other bondingtechnologies are suitable including soldering (for example, eutecticsoldering), thermo compression bonding, thermo-sonic bonding, laserbonding and/or glass reflow, and/or combinations thereof. Indeed, allforms of bonding, whether now known or later developed, are intended tofall within the scope of the present invention.

Before or after securing second substrate 14 b to first substrate 14 a,second cavity 30 may be formed in second substrate 14 b—again usingwell-known lithographic and etching techniques. In one exemplaryembodiment, second cavity 30 also includes a depth of about 11 μm.Thereafter, the thickness of second substrate 14 b may be adjusted toaccommodate further processing. For example, second substrate 14 b maybe grinded and polished (using, for example, well known chemicalmechanical polishing (“CMP”) techniques) to a thickness of between 101μm-30 μm. Notably, cavities 24 and 30 form the chamber in which themechanical structure, for example, moveable electrode 18, resides.

The second substrate 14 b may be formed from any material now known orlater developed. In a preferred embodiment, second substrate 14 bincludes or is formed from, for example, materials in column IV of theperiodic table, for example silicon, germanium, carbon; alsocombinations of these, for example silicon germanium, or siliconcarbide; also of III-V compounds for example gallium phosphide, aluminumgallium phosphide, or other III-V combinations; also combinations ofIII, IV, V, or VI materials, for example silicon nitride, silicon oxide,aluminum carbide, or aluminum oxide; also metallic silicides,germanides, and carbides, for example nickel silicide, cobalt silicide,tungsten carbide, or platinum germanium silicide; also doped variationsincluding phosphorus, arsenic, antimony, boron, or aluminum dopedsilicon or germanium, carbon, or combinations like silicon germanium;also these materials with various crystal structures, including singlecrystalline, polycrystalline, nanocrystalline, or amorphous; also withcombinations of crystal structures, for instance with regions of singlecrystalline and polycrystalline structure (whether doped or undoped).

With reference to FIG. 15E, moveable electrode 18 and contact area 26are defined and formed in second substrate 14 b. In this regard,trenches 28 a-c are formed in second substrate 14 b to define moveableelectrode 18 and contact area 26 therefrom. (See, FIG. 15E). Thetrenches 28 a-c may be formed using well-known deposition andlithographic techniques. Notably, all techniques for forming orfabricating trenches 28 a-c, whether now known or later developed, areintended to be within the scope of the present inventions.

Thereafter, third substrate 14 c may be fixed to the exposed portion(s)of second substrate 14 b. (See, FIG. 15F). The third substrate 14 c mayalso be secured to the exposed portion(s) of second substrate 14 busing, for example, well-known bonding techniques such as fusionbonding, anodic-like bonding and/or silicon direct bonding. Inconjunction with securing third substrate 14 c to second substrate 14 b,the atmosphere (including its characteristics) in which moveableelectrode 18 operates may also be defined—for example, as describedabove. Notably, all techniques of defining the atmosphere, including thepressure thereof, during the process of securing third substrate 14 c tosecond substrate 14 b, whether now known or later developed, areintended to be within the scope of the present inventions.

The third substrate 14 c may be formed from any material discussed aboverelative to second substrate 14 b. For the sake of brevity, suchdiscussions will not be repeated.

Before or after third substrate 14 c is secured to second substrate 14b, contact area 26 b may be formed in a portion of third substrate 14 cto be aligned with, connect to or overlie contact area 26 a. The contactarea 26 b may be a semiconductor region that includes a doping thatprovides the same conductivity as contact area 26 a. In this way, asuitable, desired and/or predetermined electrical conductivity isprovided with contact area 26 a when third substrate 14 c is secured tosecond substrate 14 b. (See, FIG. 15G). Thus, contact area 26 b may be ahighly doped region of third substrate 14 c which provides enhancedelectrical conductivity with contact area 26 a. The contact area 26 bmay be formed in third substrate 14 c using well-known lithographic anddoping techniques.

Notably, contact area 26 b may be a counter-doped region or heavilycounter-doped region of third substrate 14 c which includes aconductivity that is different from the conductivity of the otherportions of third substrate 14 c. In this way, contact areas 26 a and 26b are electrically isolated from the other portions of third substrate14 c. Thus, in this embodiment, second substrate 14 b may be a firstconductivity type (for example, an N-type conductivity) and thirdsubstrate 14 c may be a second conductivity type (for example, a P-typeconductivity). As such, contact area 26 b may be a counter-doped regionor heavily counter-doped N-type region which provides suitable, desiredand/or predetermined electrical conductivity characteristics when thirdsubstrate 14 c is secured to second substrate 14 b and contact areas 26a and 26 b are in physical contact.

With reference to FIG. 15H, microelectromechanical system 10 may becompleted by depositing, forming and/or growing insulation layer 32 anda contact opening may be etched to facilitate electricalcontact/connection to contact area 26 b. The conductive layer 34 (forexample, a heavily doped polysilicon, metal (such as aluminum, chromium,gold, silver, molybdenum, platinum, palladium, tungsten, titanium,and/or copper), metal stacks, complex metals and/or complex metalstacks) may then be deposited to provide the appropriate electricalconnection to contact 26 a and 26 b.

Notably, insulation layer 32 and/or conductive layer 34 may be formed,grown and/or deposited before or after third substrate 14 c is securedto second substrate 14 b. Under these circumstances, when thirdsubstrate 14 c is secured to second substrate 14 b, themicroelectromechanical system 10 may be completed.

The insulating layer 32 may be, for example, silicon dioxide, siliconnitride, BPSG, PSG, or SOG, or combinations thereof. It may beadvantageous to employ silicon nitride because silicon nitride may bedeposited in a more conformal manner than silicon oxide. Moreover,silicon nitride is compatible with CMOS processing, in the event thatmicroelectromechanical system 10 includes CMOS integrated circuits.

As mentioned above with respect to other embodiments of the presentinventions, prior to formation, deposition and/or growth of insulationlayer 32 and/or conductive layer 34, additional micromachined mechanicalstructures 12 and/or transistors of circuitry 16 may be formed and/orprovided in third substrate 14 c or in other substrates that may befixed to first substrate 14 a and/or second substrate 14 b. (See, forexample, FIGS. 16, 17 and 18 ). In this regard, the exposed surface ofthird substrate 14 c or another substrate disposed thereon may be asuitable base upon which integrated circuits (for example, CMOStransistors) (see, FIG. 16 ) and/or micromachined mechanical structures12 (see, FIGS. 17 and 18 ). Such integrated circuits and micromachinedmechanical structures 12 may be fabricated using the inventivetechniques described herein and/or well-known fabrication techniques andequipment.

For example, with reference to FIG. 16 , in one embodiment, transistorregions 36 (which may be integrated circuits (for example, CMOStransistors) of circuitry 16) may be provided in second substrate 14 b.The transistor regions 36 may be formed before or after third substrate14 c is secured (for example, bonded) to second substrate 14 b. Thefabrication techniques described above and illustrated in FIGS. 5-8B maybe employed in the embodiments of FIG. 14 . Indeed, prior to or afterformation, deposition and/or growth of insulation layer 32 and/orconductive layer 34, additional micromachined mechanical structures 12and/or transistors of circuitry 16 may be formed and/or provided insecond substrate 14 b or in other substrates that may be fixed to firstsubstrate 14 a and/or second substrate 14 b. For the sake of brevity,those discussions, in connection with the embodiments of FIG. 15 , willnot be repeated.

Notably, although second cavity 30 is described and illustrated in theprevious embodiment as being formed in second substrate 14 b, secondcavity 30 may be formed in third substrate 14 c, as illustrated in FIGS.19 and 20A-20H. Indeed, a portion of second cavity 30 may be formed insecond substrate 14 b and a portion of second cavity 30 may be formed inthird substrate 14 c.

Similarly, first cavity 24 may be formed in second substrate 14 b, asillustrated in FIG. 21 . Indeed, first cavity 24 and second cavity 30may both be formed in second substrate 14 b. (See, for example, FIG. 22). Moreover, a portion of first cavity 24 may be formed in firstsubstrate 14 a and a portion of first cavity 24 may be formed in secondsubstrate 14 b. Indeed, all permutations of formation of first cavity 24and second cavity 30 are intended to fall within the scope of thepresent inventions.

With reference to FIGS. 23-30I, in another embodiment of the presentinventions, first substrate 14 a and/or third substrate 14 c are/is thesame conductivity as second substrate 14 b. In these embodiments,micromachined mechanical structure 12 may include additional features toelectrically isolate contact 20. For example, with reference to FIG. 23, in one embodiment, second substrate 14 b is a semiconductor having thesame conductivity as the conductivity of third substrate 14 c. In thisembodiment, micromachined mechanical structure 12 includes isolationtrenches 42 a and 42 b that isolates contact 20 (and contact areas 26 aand 26 b) from portions of third substrate 14 c. In this exemplaryembodiment, the isolation trenches are aligned with isolation regions 44a and 44 b which are disposed in or on second substrate 14 b.

The isolation trenches 42 a and 42 b may include a material thatinsulates contact 20 (and contact areas 26 a and 26 b) from portions ofthird substrate 14 c. In the exemplary embodiment of FIG. 23 , aninsulating material, for example, silicon dioxide or silicon nitride, isdeposited and/or grown in isolation trenches 42 a and 42 b. Indeed, asillustrated, material that forms insulation layer 32 may also bedeposited in isolation trenches 42 a and 42 b. Notably, FIGS. 24A-24Iillustrate an exemplary process flow for fabricatingmicroelectromechanical system 10 of FIG. 23 .

As mentioned above, isolation regions 44 a and 44 b which are disposedin or on second substrate 14 b. The isolation regions 44 a and 44 b maybe any material or structure that insulates contact 20, for example, aninsulator material and/or an oppositely doped semiconductor region. Inthe exemplary embodiment of FIG. 23 , isolation regions 44 a and 44 bincludes oppositely doped semiconductor material.

With reference to FIG. 25 , in another exemplary embodiment, firstsubstrate 14 a is a semiconductor having the same conductivity as theconductivity of second substrate 14 b. In this embodiment, micromachinedmechanical structure 12 includes an isolation region 44 that isolatescontact 20 (and, in particular, contact area 26 a) from portions offirst substrate 14 a. In this exemplary embodiment, the isolation region44 is aligned with cavity 24 and trench 28 a in order to providesuitable contact isolation. The isolation region 44 may include anymaterial or structure that insulates contact 20, for example, aninsulator material and/or an oppositely doped semiconductor region. Inthe exemplary embodiment of FIG. 25 , isolation regions 44 a and 44 bincludes oppositely doped semiconductor material. Notably, FIGS. 26A-26Hillustrate an exemplary process flow for fabricatingmicroelectromechanical system 10 of FIG. 25 .

In another exemplary embodiment, first, second and third substrates 14a, 14 b and 14 c include semiconductor regions having the sameconductivity. With reference to FIG. 27 , in this embodiment,micromachined mechanical structure 12 includes an isolation trenches 42a and 42 b as well as isolation regions 44 a, 44 b, and 44 c. Theisolation trenches 42 a and 42 b, and isolation regions 44 a, 44 b, and44 c, in combination, electrically isolate contact 20 (and, inparticular, contact areas 26 a and 26 b) from contiguous portions offirst substrate 14 a and third substrates 14 c. In this exemplaryembodiment, the isolation region 44 a is aligned with cavity 24 andtrench 28 a, and isolation trenches 42 a and 42 b are aligned withisolation regions 44 b and 44 c. In this way, contact 20 includessuitable contact isolation.

The isolation trenches 42 a and 42 b may include any material thatinsulates contact 20 (and contact areas 26 a and 26 b) from portions ofthird substrate 14 c. In the exemplary embodiment of FIG. 27 , anoppositely doped semiconductor is deposited and/or grown in isolationtrenches 42 a and 42 b.

The isolation regions 44 a, 44 b and 44 c may be disposed in or on firstsubstrate 14 a and/or second substrate 14 b. In the exemplary embodimentof FIG. 27 , isolation regions 44 a and 44 b includes oppositely dopedsemiconductor material. Notably, FIGS. 28A-28I illustrate an exemplaryprocess flow for fabricating microelectromechanical system 10 of FIG. 23.

As mentioned above, isolation trenches 42 a and 42 b may include anymaterial or structure that insulates contact 20, for example, aninsulator material and/or an oppositely doped semiconductor region. Withreference to FIGS. 29 and 30A-30I, isolation trenches 42 a and 42 b mayinclude an insulating material (for example, silicon dioxide or siliconnitride) which is deposited and/or grown in isolation trenches 42 a and42 b. As illustrated, material that forms insulation layer 32 may alsobe deposited in isolation trenches 42 a and 42 b. In this regard, FIGS.30A-30I illustrate an exemplary process flow for fabricatingmicroelectromechanical system 10 of FIG. 29 .

Although not previously illustrated, the present inventions may employgrinding and polishing (using, for example, well known chemicalmechanical polishing (“CMP”) techniques at various stages in order to,for example, provide a desired surface and/or thickness. For example,with reference to FIGS. 31A-31D, where material 46 is deposited and/orgrown in isolation trenches 42 a and 42 b, the exposed surface may besubjected to grinding and polishing in order to remove a portion of thedeposited and/or grown material from the upper surface of substrate 14c. With reference to FIG. 31C, after grinding and polishing, the surfaceis prepared for further processing, for example, “back-end” processing(see, for example, FIG. 31D) or incorporation of additionalmicromachined mechanical structures 12 and/or transistors of circuitry16.

Notably, it may be advantageous to employ isolation trenches 42 andisolation regions 44 in the embodiments where substrates 14 a and 14 cinclude a conductivity that is different from the conductivity ofsubstrate 14 b. (See, for example, FIG. 32 and FIGS. 33A-33I). In thisembodiment, isolation trenches 42 and isolation regions 44 provideadditional electrical isolation for contact 20. All permutations and/orcombinations of such features are intended to fall within the scope ofthe present inventions.

The embodiments of FIGS. 23, 25, 27, 29 and 32 may also includecircuitry 16 disposed in third substrate 14 c. The fabricationtechniques described above and illustrated in FIGS. 5-8B may be employedin the embodiments of FIGS. 23, 25, 27, 29 and 32 . Indeed, prior to orafter formation, deposition and/or growth of insulation layer 32 and/orconductive layer 34, additional micromachined mechanical structures 12and/or transistors of circuitry 16 may be formed and/or provided inthird substrate 14 c or in other substrates that may be fixed to firstsubstrate 14 a and/or second substrate 14 b. For the sake of brevity,those discussions, in connection with the embodiments of FIGS. 23, 25,27, 29 and 32 , will not be repeated.

In another aspect, the present inventions may employ an insulative layerbetween the substrate in which the micromachined mechanical structures12 resides and one or more opposing or juxtaposed substrates. Such aconfiguration may provide certain processing advantages as well asenhance the electrical isolation of the micromachined mechanicalstructures 12 from one or more opposing or juxtaposed substrates. Forexample, with reference to FIG. 34 , in this exemplary embodiment,micromachined mechanical structure 12 (including moveable electrode 18and contact 20) is formed in second substrate 14 b and encapsulated viathird substrate 14 c. In this regard, micromachined mechanical structure12 is formed in a portion of substrate 14 b. Thereafter, substrate 14 cis secured (for example, bonded) to exposed surface of substrate 14 b toencapsulate micromachined mechanical structure 12. In this embodiment,insulative layers 48 a (having a thickness of about 11 μm) is disposedand patterned on first substrate 14 a to provide cavity 24 when secondsubstrate 14 b is disposed thereon. Similarly, insulative layer 48 b(having a thickness of about 11 μm) is disposed and patterned on secondsubstrate 14 b to provide cavity 30 when third substrate 14 c isdisposed thereon. Notably, substrate 14 a, 14 b and 14 c may include thesame or different conductivities.

The insulative layers 48 a and 48 b may include, for example, aninsulation material (for example, a silicon dioxide, nitride, BPSG, PSG,or SOG, or combinations thereof). It may be advantageous to employsilicon nitride because silicon nitride may be deposited, formed and/orgrown in a more conformal manner than silicon oxide. Moreover, siliconnitride is compatible with CMOS processing, in the event thatmicroelectromechanical system 10 includes CMOS integrated circuits inone or more of substrates 14 thereof.

With reference to FIGS. 35A-35C, an exemplary method of fabricating orforming micromachined mechanical structure 12 according to thisembodiment of the present inventions may begin with depositing, formingand/or growing insulative layer 48 a on first substrate 14 a.Thereafter, first cavity 24 is formed in insulative layer 48 a usingwell-known lithographic and etching techniques. The thickness andcharacteristics of insulative layer 48 a may be adjusted to accommodatefurther processing. For example, insulative layer 48 a may be polished(using, for example, well known CMP techniques) to provide a smoothplanar surface for receipt of second substrate 14 b and provide adesired depth of first cavity 24. In one exemplary embodiment, firstcavity 24 includes a depth of about 1 μm.

With reference to FIGS. 35D-35G, second substrate 14 b may be fixed toinsulative layer 48 a using, for example, well-known bonding techniquessuch as fusion bonding and/or anodic-like bonding. The insulative layer48 b may then be deposited, formed and/or grown on first substrate 14 b.The second cavity 30 may then be formed in insulative layer 48 b—againusing well-known lithographic and etching techniques. Thereafter, thethickness and characteristics of insulative layer 48 b may be adjustedto accommodate further processing. For example, insulative layer 48 bmay be polished (using, for example, well known CMP techniques) toprovide a smooth planar surface for receipt of second substrate 14 c andprovide a desired depth of second cavity 30. In one exemplaryembodiment, second cavity 24 includes a depth of about 1 μm.

In addition to forming second cavity 24 in insulative layer 48 b,contact trench window 50 is also formed therein. (See, FIG. 35G). Inthis way, trench 28 a may be formed concurrently with providing trenches28 b and 28 c which permits definition of contact are 26 a and moveableelectrode 18 simultaneously. The trenches 28 a-c may be formed usingwell-known deposition and lithographic techniques. Notably, alltechniques for forming or fabricating trenches 28 a-c, whether now knownor later developed, are intended to be within the scope of the presentinventions.

Notably, the first and second substrates 14 b may be formed from anymaterial now known or later developed. In a preferred embodiment, secondsubstrate 14 b includes or is formed from, for example, materials incolumn IV of the periodic table, for example silicon, germanium, carbon;also combinations of these, for example silicon germanium, or siliconcarbide; also of III-V compounds for example gallium phosphide, aluminumgallium phosphide, or other III-V combinations; also combinations ofIII, IV, V, or VI materials, for example silicon nitride, silicon oxide,aluminum carbide, or aluminum oxide; also metallic silicides,germanides, and carbides, for example nickel silicide, cobalt silicide,tungsten carbide, or platinum germanium silicide; also doped variationsincluding phosphorus, arsenic, antimony, boron, or aluminum dopedsilicon or germanium, carbon, or combinations like silicon germanium;also these materials with various crystal structures, including singlecrystalline, polycrystalline, nanocrystalline, or amorphous; also withcombinations of crystal structures, for instance with regions of singlecrystalline and polycrystalline structure (whether doped or undoped).

Thereafter, third substrate 14 c may be secured to the exposedportion(s) of insulative layer 48 b. (See, FIG. 35H). The thirdsubstrate 14 b may be secured using, for example, well-known bondingtechniques such as fusion bonding and/or anodic-like bonding. Inconjunction with securing third substrate 14 c to second substrate 14 b,the atmosphere (including its characteristics) in which moveableelectrode 18 operates may also be defined. Notably, all techniques ofdefining the atmosphere, including the pressure thereof, during theprocess of securing third substrate 14 c to insulative layer 48 b,whether now known or later developed, are intended to be within thescope of the present inventions.

The third substrate 14 c may be formed from any material discussed aboverelative to first substrate 14 a and/or second substrate 14 b. For thesake of brevity, such discussions will not be repeated.

With reference to FIGS. 351 and 35J, after third substrate 14 c issecured to insulative layer 48 b, contact area 26 b may be formed. Inthis regard, contact area window 52 is formed in third substrate 14 cand insulative layer 48 b to expose a portion of contact area 26 a. Suchprocessing may be performed using well-known lithographic and etchingtechniques. For example, in one embodiment, where third substrate 14 cis a semiconductor material (for example silicon), a portion of may beremoved using reactive ion etching. Thereafter, a portion of insulativelayer 48 b may be removed to expose contact area 26 b. In this regard,where insulative layer 48 b is comprised of silicon dioxide, selectedportions may be removed/etched using well-known wet etching techniquesand buffered HF mixtures (i.e., a buffered oxide etch) or well-knownvapor etching techniques using vapor HF.

The contact area 26 b may be deposited, formed and/or grown in contactarea window 52. The contact area 26 b may be an epitaxially depositedsemiconductor that includes a doping that provides the same conductivityas contact area 26 a. In this way, a suitable, desired and/orpredetermined electrical conductivity is provided with contact area 26 awhen third substrate 14 c is secured to second substrate 14 b. (See,FIG. 35K). Thus, contact area 26 b may be a highly doped polysiliconregion which provides enhanced electrical conductivity with contact area26 a.

As mentioned above, although not illustrated, the present inventions mayemploy grinding and polishing (using, for example, well known chemicalmechanical polishing (“CMP”) techniques at various stages in order to,for example, provide a desired surface and/or thickness. (See, forexample, FIGS. 31A-31D). The formation of contact area 26 b will likelyemploy such processing in order to provide the cross-sectional view ofFIG. 35K.

With reference to FIG. 35L, microelectromechanical system 10 may becompleted by depositing, forming and/or growing insulation layer 32 anda contact opening may be etched to facilitate electricalcontact/connection to contact area 26 b. The conductive layer 34 (forexample, a heavily doped polysilicon, metal (such as aluminum, chromium,gold, silver, molybdenum, platinum, palladium, tungsten, titanium,and/or copper), metal stacks, complex metals and/or complex metalstacks) may then be deposited to provide appropriate electricalconnection to contact 26 a and 26 b.

Notably, insulation layer 32 and/or conductive layer 34 may be formed,grown and/or deposited before or after third substrate 14 c is securedto second substrate 14 b. Under these circumstances, when thirdsubstrate 14 c is secured to second substrate 14 b, themicroelectromechanical system 10 may be completed.

The insulating layer 32 may be, for example, silicon dioxide, siliconnitride, BPSG, PSG, or SOG, or combinations thereof. It may beadvantageous to employ silicon nitride because silicon nitride may bedeposited in a more conformal manner than silicon oxide. Moreover,silicon nitride is compatible with CMOS processing, in the event thatmicroelectromechanical system 10 includes CMOS integrated circuits.

As mentioned above with respect to other embodiments of the presentinventions, prior to formation, deposition and/or growth of insulationlayer 32 and/or conductive layer 34, additional micromachined mechanicalstructures 12 and/or transistors of circuitry 16 may be formed and/orprovided in third substrate 14 c or in other substrates that may befixed to first substrate 14 a and/or second substrate 14 b. In thisregard, the exposed surface of third substrate 14 c or another substratedisposed thereon may be a suitable base upon which integrated circuits(for example, CMOS transistors) and/or micromachined mechanicalstructures 12. Such integrated circuits and micromachined mechanicalstructures 12 may be fabricated using the inventive techniques describedherein and/or well-known fabrication techniques and equipment. For thesake of brevity, those discussions, in connection with the embodimentsof FIGS. 34 and 35A-L, will not be repeated.

With reference to FIGS. 36 and 37A-37I, in another exemplary embodiment,microelectromechanical system 10 may be formed using at least threesubstrates 14 a-c and insulative layer 48 a disposed between substrates14 a and 14 b. In this embodiment, the portion of substrate 14 b inwhich micromachined mechanical structure 12 is formed includes a cavity(like that of previous embodiments) as well as a conductivity that isdifferent from the conductivity of the semiconductor of third substrate14 c.

Briefly, with reference to FIGS. 35A-35C, an exemplary method offabricating or forming micromachined mechanical structure 12 accordingto this embodiment of the present inventions may begin with depositing,forming and/or growing insulative layer 48 a on first substrate 14 a. Asmentioned above, insulative layer 48 a may include, for example, aninsulation material (for example, a silicon dioxide, nitride, BPSG, PSG,or SOG, or combinations thereof).

Thereafter, first cavity 24 is formed in insulative layer 48 a usingwell-known lithographic and etching techniques. (See, FIG. 37C). Thethickness and characteristics of insulative layer 48 a may be adjustedto accommodate further processing. For example, insulative layer 48 amay be polished (using, for example, well known CMP techniques) toprovide a smooth planar surface for receipt of second substrate 14 b andprovide a desired depth of first cavity 24. In one exemplary embodiment,first cavity 24 includes a depth of about 1 μm.

With reference to FIGS. 37D and 37E, second substrate 14 b may be fixedto insulative layer 48 a using, for example, well-known bondingtechniques such as fusion bonding and/or anodic-like bonding. Before orafter securing second substrate 14 b to first substrate 14 a, secondcavity 30 may be formed in second substrate 14 b using well-knownlithographic and etching techniques. In one exemplary embodiment, secondcavity 30 also includes a depth of about 11 μm. Thereafter, thethickness of second substrate 14 b may be adjusted to accommodatefurther processing. For example, second substrate 14 b may be grindedand polished (using, for example, well known chemical mechanicalpolishing (“CMP”) techniques) to a thickness of between 101 μm-30 μm.

With reference to FIG. 37F, trenches 28 a-c may be formed to definemoveable electrode 18 and contact area 26 a. The trenches may be formedusing well-known deposition and lithographic techniques. Notably, alltechniques for forming or fabricating trenches 28 a-c, whether now knownor later developed, are intended to be within the scope of the presentinventions.

The first and second substrates 14 a and 14 b may be formed from anymaterial discussed above relative to first substrate 14 a and/or secondsubstrate 14 b of other embodiments. For the sake of brevity, suchdiscussions will not be repeated.

Thereafter, third substrate 14 c may be secured to the exposedportion(s) of second substrate 14 b. (See, FIG. 35G). The thirdsubstrate 14 b may be secured using, for example, well-known bondingtechniques such as fusion bonding, anodic-like bonding and/or silicondirect bonding. In conjunction with securing third substrate 14 c tosecond substrate 14 b, the atmosphere (including its characteristics) inwhich moveable electrode 18 operates may also be defined. Notably, alltechniques of defining the atmosphere, including the pressure thereof,during the process of securing third substrate 14 c to second substrate14 b, whether now known or later developed, are intended to be withinthe scope of the present inventions.

Like first and second substrates 14 a and 14 b, third substrate 14 c maybe formed from any material discussed above relative to first, secondand/or third substrates of other embodiments. For the sake of brevity,such discussions will not be repeated.

Before or after third substrate 14 c is secured to second substrate 14b, contact area 26 b may be formed in a portion of third substrate 14 cto be aligned with, connect to or overlie contact area 26 a. The contactarea 26 b may be a semiconductor region that includes a doping thatprovides the same conductivity as contact area 26 a. In this way, asuitable, desired and/or predetermined electrical conductivity isprovided with contact area 26 a when third substrate 14 c is secured tosecond substrate 14 b. (See, FIG. 37H). Thus, contact area 26 b may be ahighly doped region of third substrate 14 c which provides enhancedelectrical conductivity with contact area 26 a. The contact area 26 bmay be formed in third substrate 14 c using well-known lithographic anddoping techniques.

Notably, contact area 26 b may be a heavily counter-doped region ofthird substrate 14 c which includes a conductivity that is differentfrom the conductivity of the other portions of third substrate 14 c. Inthis way, contact areas 26 a and 26 b are electrically isolated from theother portions of third substrate 14 c. Thus, in this embodiment, secondsubstrate 14 b may be a first conductivity type (for example, an N-typeconductivity) and third substrate 14 c may be a second conductivity type(for example, a P-type conductivity). As such, contact area 26 b may bea heavily counter-doped N-type region which provides suitable, desiredand/or predetermined electrical conductivity characteristics when thirdsubstrate 14 c is secured to second substrate 14 b and contact areas 26a and 26 b are in physical contact.

With reference to FIG. 37I, microelectromechanical system 10 may becompleted by depositing, forming and/or growing insulation layer 32 anda contact opening may be etched to facilitate electricalcontact/connection to contact area 26 b. The conductive layer 34 (forexample, a heavily doped polysilicon, metal (such as aluminum, chromium,gold, silver, molybdenum, platinum, palladium, tungsten, titanium,and/or copper), metal stacks, complex metals and/or complex metalstacks) may then be deposited to provide appropriate electricalconnection to contact 26 a and 26 b.

Notably, insulation layer 32 and/or conductive layer 34 may be formed,grown and/or deposited before or after third substrate 14 c is securedto second substrate 14 b. Under these circumstances, when thirdsubstrate 14 c is secured to second substrate 14 b, themicroelectromechanical system 10 may be completed.

The insulating layer 32 may be, for example, silicon dioxide, siliconnitride, BPSG, PSG, or SOG, or combinations thereof. It may beadvantageous to employ silicon nitride because silicon nitride may bedeposited in a more conformal manner than silicon oxide. Moreover,silicon nitride is compatible with CMOS processing, in the event thatmicroelectromechanical system 10 includes CMOS integrated circuits.

As mentioned above with respect to other embodiments of the presentinventions, prior to formation, deposition and/or growth of insulationlayer 32 and/or conductive layer 34, additional micromachined mechanicalstructures 12 and/or transistors of circuitry 16 may be formed and/orprovided in third substrate 14 c or in other substrates that may befixed to first substrate 14 a and/or second substrate 14 b. In thisregard, the exposed surface of third substrate 14 c or another substratedisposed thereon may be a suitable base upon which integrated circuits(for example, CMOS transistors) and/or micromachined mechanicalstructures 12. Such integrated circuits and micromachined mechanicalstructures 12 may be fabricated using the inventive techniques describedherein and/or well-known fabrication techniques and equipment. For thesake of brevity, those discussions, in connection with the embodimentsof FIGS. 36 and 37A-I, will not be repeated.

In this embodiment, the portion of substrate 14 b in which micromachinedmechanical structure 12 is formed includes a conductivity that is thesame as the conductivity of the semiconductor of third substrate 14 c.In this embodiment, micromachined mechanical structure 12 includes anisolation trenches 42 a and 42 b as well as isolation regions 44 a and44 b. The isolation trenches 42 a and 42 b, and isolation regions 44 aand 44 b, in combination, electrically isolate contact (and, inparticular, contact areas 26 a and 26 b) from contiguous portions ofthird substrate 14 c. In this exemplary embodiment, isolation region 44a is aligned with cavity 24 and trench 28 a, and isolation trenches 42 aand 42 b are aligned with isolation regions 44 b and 44 c. In this way,contact includes suitable contact isolation.

Briefly, with reference to FIGS. 39A-39D and 39F, an exemplary method offabricating or forming micromachined mechanical structure 12 accordingto this embodiment of the present inventions may be substantially thesame as with the previous embodiment. For the sake of brevity thosediscussions will not be repeated.

With reference to FIG. 39E, in this embodiment, isolation regions 44 aand 44 b are deposited and/or implanted into portions of substrate 14 bin order to facilitate electrical isolation of contact 20 after secondsubstrate 14 b is secured or fixed (via, for example, bonding). Theisolation regions 44 a and 44 b may be any material or structure thatinsulates contact 20, for example, an insulator material and/or anoppositely doped semiconductor region. In the illustrative example,isolation regions 44 a and 44 b are oppositely doped semiconductorregion (relative to the conductivity of substrate 14 c).

With reference to FIG. 39F, trenches 28 a-c may be formed to definemoveable electrode 18 and contact area 26 a. The trenches may be formedusing well-known deposition and lithographic techniques. Notably, alltechniques for forming or fabricating trenches 28 a-c, whether now knownor later developed, are intended to be within the scope of the presentinventions.

Thereafter, third substrate 14 c may be secured to the exposedportion(s) of second substrate 14 b. (See, FIG. 39G). The thirdsubstrate 14 b may be secured using, for example, well-known bondingtechniques such as fusion bonding, anodic-like bonding and/or silicondirect bonding. In conjunction with securing third substrate 14 c tosecond substrate 14 b, the atmosphere (including its characteristics) inwhich moveable electrode 18 operates may also be defined. Notably, alltechniques of defining the atmosphere, including the pressure thereof,during the process of securing third substrate 14 c to second substrate14 b, whether now known or later developed, are intended to be withinthe scope of the present inventions.

Thereafter, isolation trenches 42 a and 42 b are formed in portions ofthird substrate 14 c. (See, FIG. 39H). The isolation trenches 42 a and42 b may be formed using well-known lithographic and etching techniques.In this exemplary embodiment, the isolation trenches are aligned withisolation regions 44 a and 44 b which are disposed in or on secondsubstrate 14 b.

With reference to FIG. 39I, isolation trenches 42 a and 42 b may includea material that insulates contact 20 (and contact areas 26 a and 26 b)from portions of third substrate 14 c. In the exemplary embodiment, aninsulating material, for example, silicon dioxide or silicon nitride, isdeposited and/or grown in isolation trenches 42 a and 42 b. Indeed, asillustrated, material that forms insulation layer 32 may also bedeposited in isolation trenches 42 a and 42 b. Notably, isolationtrenches 42 a and 42 b may include any material that insulates contact20 (and contact areas 26 a and 26 b) from portions of third substrate 14c.

With reference to FIG. 39I-39K, microelectromechanical system 10 may becompleted by depositing, forming and/or growing insulation layer 32 anda contact opening may be etched to facilitate electricalcontact/connection to contact area 26 b. The processing may be the sameor similar to that described herein with any of the other embodiments.For the sake of brevity, those discussions will not be repeated.

Moreover, as mentioned above with respect to other embodiments of thepresent inventions, prior to formation, deposition and/or growth ofinsulation layer 32 and/or conductive layer 34, additional micromachinedmechanical structures 12 and/or transistors of circuitry 16 may beformed and/or provided in third substrate 14 c or in other substratesthat may be fixed to first substrate 14 a and/or second substrate 14 b.In this regard, the exposed surface of third substrate 14 c or anothersubstrate disposed thereon may be a suitable base upon which integratedcircuits (for example, CMOS transistors) and/or micromachined mechanicalstructures 12. Such integrated circuits and micromachined mechanicalstructures 12 may be fabricated using the inventive techniques describedherein and/or well-known fabrication techniques and equipment. For thesake of brevity, those discussions, in connection with the embodimentsof FIGS. 38 and 39A-K, will not be repeated.

In another embodiment, with reference to FIG. 40 , after formation ofcavity 18 in first substrate 14 a, intermediate layer 54 is deposited orgrown before second substrate 148 is secured to first substrate 14 a. Inone embodiment, intermediate layer 54 may be a native oxide. In anotherembodiment, a thin insulating layer is deposited. In this way, firstsubstrate 14 a is electrically isolated from second substrate 14 b.Thereafter, second substrate 14 b may be fixed to intermediate layer 54using, for example, well-known bonding techniques such as fusion bondingand/or anodic-like bonding. Before or after securing second substrate 14b to first substrate 14 a, second cavity 30 may be formed in secondsubstrate 14 b using well-known lithographic and etching techniques. Inone exemplary embodiment, second cavity 30 also includes a depth ofabout 11 μm. Thereafter, the thickness of second substrate 14 b may beadjusted to accommodate further processing. For example, secondsubstrate 14 b may be grinded and polished (using, for example, wellknown chemical mechanical polishing (“CMP”) techniques) to a thicknessof between 101 μm-30 μm.

FIGS. 41A-41H illustrate an exemplary process flow for fabricatingmicroelectromechanical system 10 of FIG. 23 . For the sake of brevity,the exemplary process flow will not be discussed in detail; referencehowever, is made to the discussions above.

The embodiment including intermediate layer 54 may be employed inconjunction with any of the embodiments described herein. (See, forexample, FIGS. 42A and 42B, 43A-43K). For the sake of brevity, theexemplary process flow will not be discussed in detail; referencehowever, is made to the discussions above.

There are many inventions described and illustrated herein. Whilecertain embodiments, features, materials, configurations, attributes andadvantages of the inventions have been described and illustrated, itshould be understood that many other, as well as different and/orsimilar embodiments, features, materials, configurations, attributes,structures and advantages of the present inventions that are apparentfrom the description, illustration and claims (are possible by oneskilled in the art after consideration and/or review of thisdisclosure). As such, the embodiments, features, materials,configurations, attributes, structures and advantages of the inventionsdescribed and illustrated herein are not exhaustive and it should beunderstood that such other, similar, as well as different, embodiments,features, materials, configurations, attributes, structures andadvantages of the present inventions are within the scope of the presentinventions.

Each of the aspects of the present inventions, and/or embodimentsthereof, may be employed alone or in combination with one or more ofsuch aspects and/or embodiments. (See, for example, FIGS. 42A and 42B,43A-43K). For the sake of brevity, those permutations and combinationswill not be discussed separately herein. As such, the present inventionsare not limited to any single aspect or embodiment thereof nor to anycombinations and/or permutations of such aspects and/or embodiments.

Notably, it may be advantageous to adjust the alignment and etchprocesses to enhance electrical isolation of portions of micromachinedmechanical structure 12, for example, contact 20 (including contactareas 26 a and 26 b). For example, with reference to FIG. 44 , trench 28a may be aligned to provide suitable or predetermined overlap ofisolation region 44 a and 44 b as well as include suitable orpredetermined over etch into isolation region 44 a. Further, isolationregion 44 c may include dimensions such that when cavity 30 is formed, aportion of isolation region 44 c is removed. (See, FIGS. 45C and 45D).Moreover, with reference to FIG. 46A, isolation trenches 42 a and 42 bmay include suitable or predetermined over etch into isolation regions44 a and 44 b. Indeed, isolation trench 28 a may be substantially largerand/or have considerably different tolerances than trenches 28 b and 28c given that the dimensions of the trench are insignificant relative totrenches 28 b and 28 c which may largely define the mechanical structureof the system 10. (See, FIG. 46B). Such processing techniques may beapplied to any of the embodiments described and/or illustrated herein.

Further, the processing flows described and illustrated herein areexemplary. These flows, and the order thereof, may be modified. Allprocess flows, and orders thereof, to provide microelectromechanicalsystem 10 and/or micromachined mechanical structure 12, whether nowknown or later developed, are intended to fall within the scope of thepresent inventions. For example, there are many techniques to formmoveable electrode 18 and contact 20 (and in particular contact area 26a). With reference to FIG. 47A-47D, in one embodiment, mask 56 a may bedeposited and patterned. Thereafter, cavity 30 may be formed (See, FIGS.47A and 47B). Thereafter, mask 56 b may be deposited and patterned inorder to form and define moveable electrode 18 and contact area 26 (See,FIGS. 47C and 47D).

Alternatively, with reference to FIGS. 48A-48C, masks 56 a and 56 b maybe deposited and patterned. After trenches 28 a-28 c are formed, mask 56b may be removed and cavity 30 may be formed.

Further, substrates 14 may be processed to a predetermined and/orsuitable thickness before and/or after other processing during thefabrication of microelectromechanical system 10 and/or micromachinedmechanical structure 12. For example, with reference to FIGS. 49A-49G,in one embodiment, first substrate 14 a may be a relatively thick waferwhich is grinded (and polished) after substrates 14 b and 14 c aresecured to a corresponding substrate (for example, bonded) and processedto form, for example, micromachined mechanical structure 12. (Compare,for example, FIGS. 49A-G and 49H).

The processing flows described and illustrated with respect to substrate14 c may also be modified. For example, with reference to FIGS. 50A-50G,in one embodiment, substrate 14 c may be a relatively thick wafer whichis grinded (and polished) after secured to a corresponding substrate(for example, bonded). In this exemplary embodiment, substrate 14 c isgrinded and polished after being bonded to substrate 14 b. (Compare, forexample, FIGS. 50C and 50D) Thereafter, contact 20 may be formed. (See,for example, FIGS. 50E-50G).

Indeed, substrate 14 a and 14 c may be processed (for example, grindedand polished) after other processing. (See, for example, FIGS. 51A-51J).Notably, all processing flows with respect to substrates 14 are intendedto fall within the scope of the present invention.

Further, as mentioned above, each of the aspects of the presentinventions, and/or embodiments thereof, may be employed alone or incombination with one or more of such aspects and/or embodiments. Forexample, with reference to FIG. 52 , microelectromechanical system mayinclude implant regions 58 a and 58 b in substrate 14 c to facilitateelectrically isolation of contact area 26 b from other portions ofsubstrate 14 c. In this embodiment implant regions 58 a and 58 b may beany material or structure that insulates contact 20, for example, anoppositely doped semiconductor region. FIGS. 53A-53H illustrate anexemplary process flow for fabricating microelectromechanical system 10of FIG. 52 wherein implant regions 58 a and 58 b are oppositely dopedsemiconductor regions.

Notably, implant regions 58 a and 58 b may be employed in any of theembodiments described and illustrated herein. For example, the implantregions 58 a and 58 b may be employed in conjunction with or in lieu ofisolation trenches 42 a and 42 b.

In addition, as mentioned above, isolation regions 44 a and 44 b may bedeposited and/or implanted into portions of substrate 14 b in order tofacilitate electrical isolation of contact 20 after third substrate 14 c(or second substrate 14 b where an SOI substrate 14 a is employed (see,FIG. 11 )) is secured or fixed (via, for example, bonding). Theisolation regions 44 a and 44 b may be any material or structure thatinsulates contact 20, for example, an insulation material and/or anoppositely doped semiconductor region. FIGS. 55A-55K illustrate anexemplary process flow for fabricating microelectromechanical system 10of FIG. 54 wherein isolation regions 44 a and 44 b are insulationmaterial (for example, a silicon nitride or silicon dioxide) and aninsulation material is disposed in isolation trenches 42 a and 42 b.

Further, as an alternative to counter-doping a region in substrate 14 cto form contact area 26 b, with reference to FIG. 56 and FIGS. 57A-57J,contact area 26 b may be formed by providing a “window” in substrate 14c (for example, etching a portion of substrate 14 c as illustrated inFIG. 57H) and thereafter depositing a suitable material to provideelectrical conductivity with the underlying contact area 26 a. Notably,the material (for example, a doped polysilicon) which forms contact area26 b may be deposited by epitaxial deposition and thereafter planarizedto provide a suitable surface for contact 20 formation. (See, forexample, FIGS. 57H and 571 ).

As mentioned above, all forms of bonding, whether now known or laterdeveloped, are intended to fall within the scope of the presentinvention. For example, bonding techniques such as fusion bonding,anodic-like bonding, silicon direct bonding, soldering (for example,eutectic soldering), thermo compression, thermo-sonic bonding, laserbonding and/or glass reflow bonding, and/or combinations thereof.

Notably, any of the embodiments described and illustrated herein mayemploy a bonding material and/or a bonding facilitator material(disposed between substrates, for example, the second and thirdsubstrates) to, for example, enhance the attachment of or the “seal”between the substrates (for example, between the first and secondsubstrates 14 a and 14 b, and/or the second and third substrates 14 band 14 c), address/compensate for planarity considerations betweensubstrates to be bonded (for example, compensate for differences inplanarity between bonded substrates), and/or to reduce and/or minimizedifferences in thermal expansion (that is materials having differentcoefficients of thermal expansion) of the substrates and materialstherebetween (if any). Such materials may be, for example, solder,metals, frit, adhesives, BPSG, PSG, or SOG, or combinations thereof.

With reference to FIG. 58 , in one exemplary embodiment, bondingmaterial or bonding facilitator material 60 may be disposed betweensubstrates 14 b and 14 c. Such a configuration may provide certainadvantages. For example, in this exemplary embodiment, micromachinedmechanical structure 12 (including moveable electrode 18 and contact 20)is formed in second substrate 14 b and encapsulated via third substrate14 c. In this regard, micromachined mechanical structure 12 is formed ina portion of substrate 14 b. Thereafter, substrate 14 c is secured (forexample, bonded) to exposed surface of substrate 14 b to encapsulatemicromachined mechanical structure 12. In this embodiment, bondingmaterial or bonding facilitator material 60 (for example, having athickness of about 11 μm) is disposed and patterned on second substrate14 b to provide cavity 30 when third substrate 14 c is disposed thereonand bonded thereto. Notably, substrates 14 a, 14 b and 14 c may includethe same or different conductivities.

As mentioned above, bonding material or bonding facilitator material 60may include, for example, solder, metals, frit, adhesives, BPSG, PSG, orSOG, or combinations thereof. It may be advantageous to employ BPSG,PSG, or SOG in order to electrically isolate contact 20 from portions ofsubstrates 14 b and/or 14 c. Moreover, BPSG, PSG, or SOG is compatiblewith CMOS processing, in the event that microelectromechanical system 10includes CMOS integrated circuits in one or more of substrates 14thereof.

Notably, FIGS. 59A-59J illustrate an exemplary process flow forfabricating microelectromechanical system 10 of FIG. 58 . The processflow may employ a flow which is substantially similar to the process ofFIGS. 35A-35L—with the exception that bonding material or bondingfacilitator material 60 is employed (deposited and patterned) inaddition to or in lieu of insulative layer 48 b of FIGS. 35E-35L. Forthe sake of brevity, the discussion will not be repeated here.

An alternative embodiment employing bonding material or bondingfacilitator material 60, and technique for fabricating such embodiment,is illustrated in FIGS. 60 and 61A-61K, respectively. In thisembodiment, bonding material and/or a bonding facilitator material 60 isprovided prior to formation of resonator 18 and contact area 26 a (viacontact area trench 28 a and moveable electrode trenches 28 b and 28 c).As mentioned above, all process flows, and orders thereof, to providemicroelectromechanical system 10 and/or micromachined mechanicalstructure 12, whether now known or later developed, are intended to fallwithin the scope of the present inventions.

The embodiments employing bonding material or bonding facilitatormaterial 60 may be implemented in any of the embodiments describedherein. For example, transistors of a transistor region may be formedprior to securing third substrate 14 c to second substrate 14 b. (See,for example, FIGS. 7A and 7B). Indeed, all of the “back-end” processing,in addition to formation of the transistors of transistor region, may becompleted prior to securing third substrate 14 c to second substrate 14b. (See, for example, FIGS. 8A and 8B).

Moreover, any of the bonding material or bonding facilitator materials60 (may include, for example, solder, metals, frit, adhesives, BPSG,PSG, or SOG, or combinations thereof) may be implemented between thefirst and second substrates 14 a and 14 b, and/or the second and thirdsubstrates 14 b and 14 c, and/or any other substrates that are bonded.All such permutations are intended to fall within the scope of thepresent inventions.

Further, with respect to any of the embodiments described herein,circuitry 16 may be integrated in or on substrate 14, disposed in aseparate substrate, and/or in one or more substrates that are connectedto substrate 14 (for example, in one or more of the encapsulationwafer(s)). (See, for example, FIGS. 62-64 ). In this regard,microelectromechanical device 10 may include micromachined mechanicalstructure 12 and circuitry 16 as a monolithic-like structure includingmechanical structure 12 and circuitry 16 in one substrate.

The micromachined mechanical structure 12 and/or circuitry 16 may alsoreside on separate, discrete substrates. (See, for example, FIGS. 65 and66A-66F). In this regard, in one embodiment, such separate discretesubstrate may be bonded to or on substrate 14, before, during and/orafter fabrication of micromachined mechanical structure 12 and/orcircuitry 16. (See, for example FIGS. 5, 6A-6D, 7A-7C and 8A).

For example, as mentioned above, the electronics or electrical circuitrymay be clock alignment circuitry, for example, one or more phase lockedloops (PLLs), delay locked loops (DLLs), digital/frequency synthesizer(for example, a direct digital synthesizer (“DDS”), frequencysynthesizer, fractional synthesizer and/or numerically controlledoscillator) and/or frequency locked loops (FLLs). In this regard, theoutput of mechanical structure 12 (for example, anmicroelectromechanical oscillator or microelectromechanical resonator)is employed as a reference input signal (i.e., the reference clock). ThePLL, DLL, digital/frequency synthesizer and/or FLL may provide frequencymultiplication (i.e., increase the frequency of the output signal of themicroelectromechanical oscillator). The PLL, DLL, digital/frequencysynthesizer and/or FLL may also provide frequency division (i.e.,decrease the frequency of the output signal of themicroelectromechanical oscillator). Moreover, the PLL, DLL,digital/frequency synthesizer and/or FLL may also compensate usingmultiplication and/or division to adjust, correct, compensate and/orcontrol the characteristics (for example, the frequency, phase and/orjitter) of the output signal of the microelectromechanical resonator.

The multiplication or division (and/or phase adjustments) bycompensation circuitry 17 may be in fine or coarse increments. Forexample, compensation circuitry 17 may include an integer PLL, afractional PLL and/or a fine-fractional-N PLL to precisely select,control and/or set the output signal of compensatedmicroelectromechanical oscillator. In this regard, the output ofmicroelectromechanical resonator may be provided to the input of thefractional-N PLL and/or the fine-fractional-N PLL (hereinaftercollectively “fractional-N PLL”), which may be pre-set, pre-programmedand/or programmable to provide an output signal having a desired,selected and/or predetermined frequency and/or phase.

Notably, in one embodiment, the parameters, references (for example,frequency and/or phase), values and/or coefficients employed by thecompensation circuitry in order to generate and/or provide an adjusted,corrected and/or controlled output having, for example, a desired,selected and/or predetermined frequency and/or phase (i.e., the functionof the compensation circuitry), may be externally provided to thecompensation circuitry either before or during operation of compensatedmicroelectromechanical oscillator. In this regard, a user or externalcircuitry/devices/systems may provide information representative of theparameters, references, values and/or coefficients to set, change,enhance and/or optimize the performance of the compensation circuitryand/or compensated microelectromechanical oscillator.

Finally, it should be further noted that while the present inventionswill be described in the context of microelectromechanical systemsincluding micromechanical structures or elements, the present inventionsare not limited in this regard. Rather, the inventions described hereinare applicable to other electromechanical systems including, forexample, nanoelectromechanical systems. Thus, the present inventions arepertinent, as mentioned above, to electromechanical systems, forexample, gyroscopes, resonators, temperatures sensors, accelerometersand/or other transducers.

The term “depositing” and other forms (i.e., deposit, deposition anddeposited) in the claims, means, among other things, depositing,creating, forming and/or growing a layer of material using, for example,a reactor (for example, an epitaxial, a sputtering or a CVD-basedreactor (for example, APCVD, LPCVD, or PECVD)).

Further, in the claims, the term “contact” means a conductive region,partially or wholly disposed outside the chamber, for example, thecontact area and/or contact via.

It should be further noted that the term “circuit” may mean, among otherthings, a single component or a multiplicity of components (whether inintegrated circuit form or otherwise), which are active and/or passive,and which are coupled together to provide or perform a desired function.The term “circuitry” may mean, among other things, a circuit (whetherintegrated or otherwise), a group of such circuits, one or moreprocessors, one or more state machines, one or more processorsimplementing software, or a combination of one or more circuits (whetherintegrated or otherwise), one or more state machines, one or moreprocessors, and/or one or more processors implementing software. Theterm “data” may mean, among other things, a current or voltage signal(s)whether in an analog or a digital form.

The embodiments of the inventions described herein may include one ormore of the following advantages, among others:

-   -   embodiments presenting mechanically robust encapsulation;    -   embodiments presenting clean environment for micromachined        mechanical structure 12 (and the electrodes thereof);    -   embodiments presenting relatively less expensive fabrication in        comparison to conventional techniques;    -   embodiments presenting relatively smaller footprint in        comparison to conventional techniques;    -   embodiments presenting one or more surfaces compatible with/for        CMOS circuitry/integration;    -   embodiments presenting single crystal surfaces (where one or        more substrates are single crystal);    -   embodiments presenting diffused contacts;    -   embodiments eliminating epitaxial depositions;    -   embodiments eliminating SOI substrates;    -   embodiments presenting improved CMOS compatibility;    -   embodiments providing enhanced atmosphere/environment control        and characteristics (for example, improved vacuum and lower/no        chlorine;    -   improved gap control for definition of micromachined mechanical        structure;    -   embodiments eliminating timed release of moveable electrodes        (for example, timed HF (vapor) etch);    -   embodiments eliminating oxide stress in substrates;    -   embodiments providing enhanced stiction characteristics (for        example, less vertical stiction); and    -   embodiments eliminating vents in the resonator and the attendant        shortcomings of thin film encapsulation.

The above embodiments of the present inventions are merely exemplaryembodiments. They are not intended to be exhaustive or to limit theinventions to the precise forms, techniques, materials and/orconfigurations disclosed. Many modifications and variations are possiblein light of the above teaching. It is to be understood that otherembodiments may be utilized and operational changes may be made withoutdeparting from the scope of the present inventions. As such, theforegoing description of the exemplary embodiments of the inventions hasbeen presented for the purposes of illustration and description. It isintended that the scope of the inventions not be limited to thedescription above.

1. (canceled)
 2. A device comprising: a first substrate; a secondsubstrate; in between the first substrate and the second substrate, atleast intermediate layer, the at least one intermediate layer comprisinga semiconductor layer patterned to defined a microelectromechanicalsystems (MEMS) resonant structure, the at least one intermediate layeralso providing a frame that encircles the MEMS resonant structure;wherein the first substrate, the second substrate and the framecooperate to hermetically seal the MEMS resonant structure within aninterior chamber of said device; and one or more electrical contacts onan exterior of said device, to provide an output signal representing aresonance frequency of the MEMS resonant structure.
 3. The device ofclaim 2 wherein the second substrate is bonded to an outermost layer ofthe at least one intermediate layer, in a manner such that a bondinginterface is defined at a region of contact between the second substrateand the outermost layer.
 4. The device of claim 2 wherein: the secondsubstrate has a first surface, which faces towards the first substrate,and a second surface, which faces away from the first substrate: the atleast one intermediate layer comprises an electrode which lies inbetween the first substrate and the first surface; the one or moreelectrical contacts comprise a contact mounted by the second surface;and the device comprises an electrical pathway which conductivelyconnects the electrode with the contact mounted by the second surface.5. The device of claim 4 wherein: the MEMS structure and the electricalpathway each comprise respective, doped portions of a commonsemiconductor layer between the first substrate and the secondsubstrate; and the respective, doped portions comprise a commonly-dopedlayer of silicon that is patterned so as to form part of the MEMSstructure and part of the electrical pathway.
 6. The device of claim 5wherein the respective, doped portions of the common semiconductor layercomprise a silicon layer of a silicon-on-insulator wafer, heavily dopedwith at least one of phosphorus or antimony, and wherein the chamber isat least partially formed by a volume corresponding to a section ofinsulator material that has been removed from the silicon-on-insulatorwafer.
 7. The device of claim 5 wherein the common semiconductor layercomprises single crystal silicon.
 8. The device of claim 2 wherein thechamber defines a partial vacuum relative to an ambient atmosphereexternal to said device.
 9. The device of claim 2 wherein the firstsubstrate and the second substrate each are composed primarily ofsilicon.
 10. The device of claim 2 wherein at least one of the firstsubstrate or the second substrate is bonded relative to the other via atleast one of a metallic bond, an anodic bond or a glass frit bond. 11.The device of claim 2 wherein the one or more intermediate layerscomprises at least one insulator layer.
 12. A method of manufacturing adevice, the method comprising: providing a first substrate; forming atleast intermediate layer to lie above the first substrate, whereinforming comprises patterning a semiconductor layer to defined amicroelectromechanical systems (MEMS) resonant structure, and providinga frame that encircles the MEMS resonant structure; providing a secondsubstrate to lie above the first substrate and the at least oneintermediate layer, such that the first substrate, the second substrateand the frame cooperate to hermetically seal the MEMS resonant structurewithin an interior chamber of said device; and forming one or moreelectrical contacts on an exterior of said device, to provide an outputsignal representing a resonance frequency of the MEMS resonantstructure.
 13. An integrated circuit device comprising: a firstsubstrate; a second substrate; in between the first substrate and thesecond substrate, at least intermediate layer, the at least oneintermediate layer comprising a semiconductor layer patterned to defineda microelectromechanical systems (MEMS) resonant structure, the at leastone intermediate layer also providing a frame that encircles the MEMSresonant structure; and a substrate supporting at least onecomplementary metal oxide semiconductor (CMOS) device.